Inroads to the Unharnessed Power Savings of Asynchronous Chip Design

Asynchronous chip design is an emerging technology that behooves both technical professionals and laymen alike to encounter. The power consumed by chips for our daily computational needs stirs up a variety of issues and reasons for taking an interest in technologies which reduce that power consumption. Asynchronous chip design is one of those technologies.

Bernd Hoefflinger, author of CHIPS 2020: A Guide to the Future of Nanoelectronics, recently communicated the importance of chip-power-consumption with force, observing that the world’s 6 billion people will soon be expecting “communication at the video level.” However, Hoefflinger goes on to observe, with current technologies, “we would eat up the world’s total electric power within five years,” in an effort to accomplish the orders-of-magnitude increases in calculations required to support the data streams associated with such expectations. Furthermore, as Moore’s law marches forward, namely, that the computational components for a given area of chip roughly doubles every two years, the exponential increases in the number of components drawing power in a given area causes chips to heat up to the point where cooling chips and reducing power is one of, if not the, greatest obstacle to continued increases in chip performance. Burgeoning power demands required to meet computational needs also have broader implications for seemingly unrelated issues, such as environmental issues. Also, the implications for battery life, as mobile devices become a ubiquitous fact of daily life, almost goes without saying.

Asynchronously designed chips, however, consistently demonstrate a three-fold reduction in energy usage. Indeed, for some time, industry and academic institutions have predicted the technology to play a pivotal role in reducing problems associated with high power consumption, from environmental issues, to high power bills, to impediments to the continued progression of computational performance. A brief explanation is sufficient to understand these substantial power related benefits of asynchronous chip design.

Computer chips process data sequentially, in a manner that requires certain processing steps to be completed before other steps get underway. If one step begins before another step on which it relies has an opportunity to finish, an error results. Traditionally, these steps are synchronized by the on-again, off-again beat of a common clock signal. However, enormous amounts of power are lost, not only generating and propagating a signal from a clock throughout an entire integrated circuit, but also because, more importantly, the various stages in a synchronous design dissipate power during each clock cycle, whether they are actively computing or not.

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